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1. general description the 74lvc2g00 provides a 2-input nand gate function. inputs can be driven from either 3.3 v or 5 v devices. this feature allows the use of these devices as translators in a mixed 3.3 v and 5 v environment. this device is fully specified for pa rtial power-down ap plications using i off . the i off circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. features and benefits ? wide supply voltage range from 1.65 v to 5.5 v ? 5 v tolerant outputs for interfacing with 5 v logic ? high noise immunity ? 24 ma output drive (v cc =3.0v) ? cmos low power consumption ? complies with jedec standard: ? jesd8-7 (1.65 v to 1.95 v) ? jesd8-5 (2.3 v to 2.7 v) ? jesd8-b/jesd36 (2.7 v to 3.6 v) ? latch-up performance exceeds 250 ma ? direct interface with ttl levels ? inputs accept voltages up to 5 v ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v ? multiple package options ? specified from ? 40 cto +85 c and ? 40 cto+125 c 74lvc2g00 dual 2-input nand gate rev. 09 ? 8 june 2010 product data sheet
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 2 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. table 1. ordering information type number package temperature range name description version 74lvc2g00dp ? 40 c to +125 c tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505-2 74lvc2g00dc ? 40 c to +125 c vssop8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm sot765-1 74lvc2g00gt ? 40 c to +125 c xson8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 1.95 0.5 mm sot833-1 74LVC2G00GF ? 40 c to +125 c xson8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1 0.5 mm sot1089 74lvc2g00gd ? 40 c to +125 c xson8u plastic extremely thin small outline package; no leads; 8 terminals; utlp based; body 3 2 0.5 mm sot996-2 74lvc2g00gm ? 40 c to +125 c xqfn8u plastic extremely thin quad flat package; no leads; 8 terminals; utlp based; body 1.6 1.6 0.5 mm sot902-1 74lvc2g00gn ? 40 c to +125 c xson8 extremely thin small outline package; no leads; 8 terminals; body 1.2 1.0 0.35 mm sot1116 74lvc2g00gs ? 40 c to +125 c xson8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1.0 0.35 mm sot1203 table 2. marking codes type number marking code [1] 74lvc2g00dp v2g00 74lvc2g00dc v00 74lvc2g00gt v00 74LVC2G00GF va 74lvc2g00gd v00 74lvc2g00gm v00 74lvc2g00gn va 74lvc2g00gs va
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 3 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 5. functional diagram 6. pinning information 6.1 pinning fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) 001aah748 1a 1b 1y 2a 2b 2y 001aah749 & & mna099 b a y fig 4. pin configuration sot505-2 and sot765-1 fig 5. pin configuration sot833-1, sot1089, sot1116 and sot1203 74lvc2g00 1a v cc 1b 1y 2y 2b gnd 2a 001aab736 1 2 3 4 6 5 8 7 74lvc2g00 2b 1y v cc 2a 2y 1b 1a gnd 001aab73 7 36 27 18 45 transparent top view fig 6. pin configuration sot996-2 f ig 7. pin configuration sot902-1 001aai251 74lvc2g00 transparent top view 8 7 6 5 1 2 3 4 1a 1b 2y gnd v cc 1y 2b 2a 001aae9 80 1b 2b 1a v cc 2y 1y gnd 2a transparent top view 3 6 4 1 5 8 7 2 terminal 1 index area 74lvc2g00
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 4 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level. 8. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] when v cc = 0 v (power-down mode), the output voltage can be 5.5 v in normal operation. [3] for tssop8 package: above 55 c the value of p tot derates linearly with 2.5 mw/k. for vssop8 package: above 110 c the value of p tot derates linearly with 8 mw/k. for xson8, xson8u and xqfn8u packages: above 118 c the value of p tot derates linearly with 7.8 mw/k. table 3. pin description symbol pin description sot505-2, sot765-1, sot833-1, sot1089, sot996-2, sot1116 and sot1203 sot902-1 1a, 2a 1, 5 7, 3 data input 1b, 2b 2, 6 6, 2 data input gnd 4 4 ground (0 v) 1y, 2y 7, 3 1, 5 data output v cc 8 8 supply voltage table 4. function table [1] input output na nb ny llh lhh hl h hhl table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v v i input voltage [1] ? 0.5 +6.5 v v o output voltage active mode [1] ? 0.5 v cc + 0.5 v power-down mode [1] [2] ? 0.5 +6.5 v i ik input clamping current v i <0v ? 50 - ma i ok output clamping current v o <0v or v o >v cc - 50 ma i o output current v o =0vtov cc - 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 c p tot total power dissipation t amb = ? 40 c to +125 c [3] - 300 mw
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 5 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 9. recommended operating conditions 10. static characteristics table 6. operating conditions symbol parameter conditions min max unit v cc supply voltage 1.65 5.5 v v i input voltage 0 5.5 v v o output voltage active mode 0 v cc v power-down mode 0 5.5 v t amb ambient temperature ? 40 +125 c t/ v input transition rise and fall rate v cc =1.65v to2.7v - 20 ns/v v cc = 2.7 v to 5.5 v - 10 ns/v table 7. static characteristics at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = ? 40 c to +85 c [1] v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.7 - - v v cc = 2.7 v to 3.6 v 2.0 - - v v cc = 4.5 v to 5.5 v 0.7 v cc -- v v il low-level input voltage v cc = 1.65 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 v v cc = 4.5 v to 5.5 v - - 0.3 v cc v v oh high-level output voltage v i =v ih or v il i o = ? 100 a; v cc = 1.65 v to 5.5 v v cc ? 0.1 - - v i o = ? 4 ma; v cc =1.65v 1.2 1.53 - v i o = ? 8 ma; v cc = 2.3 v 1.9 2.13 - v i o = ? 12 ma; v cc = 2.7 v 2.2 2.50 - v i o = ? 24 ma; v cc = 3.0 v 2.3 2.60 - v i o = ? 32 ma; v cc = 4.5 v 3.8 4.10 - v v ol low-level output voltage v i = v ih or v il i o = 100 a; v cc = 1.65 v to 5.5 v - - 0.1 v i o = 4 ma; v cc = 1.65 v - 0.08 0.45 v i o = 8 ma; v cc = 2.3 v - 0.14 0.3 v i o = 12 ma; v cc = 2.7 v - 0.19 0.4 v i o = 24 ma; v cc = 3.0 v - 0.37 0.55 v i o = 32 ma; v cc = 4.5 v - 0.43 0.55 v i i input leakage current v i = 5.5 v or gnd; v cc =0vto5.5v - 0.1 5 a i off power-off leakage current v i or v o = 5.5 v; v cc = 0 v - 0.1 10 a
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 6 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate [1] all typical values are measured at t amb = 25 c. i cc supply current v i = 5.5 v or gnd; v cc =1.65vto5.5v; i o =0a -0.110 a i cc additional supply current per pin; v i = v cc ? 0.6 v; i o = 0 a; v cc = 2.3 v to 5.5 v -5500 a c i input capacitance - 2.5 - pf t amb = ? 40 c to +125 c v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.7 - - v v cc = 2.7 v to 3.6 v 2.0 - - v v cc = 4.5 v to 5.5 v 0.7 v cc -- v v il low-level input voltage v cc = 1.65 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 v v cc = 4.5 v to 5.5 v - - 0.3 v cc v v oh high-level output voltage v i =v ih or v il i o = ? 100 a; v cc = 1.65 v to 5.5 v v cc ? 0.1 - - v i o = ? 4 ma; v cc = 1.65 v 0.95 - - v i o = ? 8 ma; v cc = 2.3 v 1.7 - - v i o = ? 12 ma; v cc = 2.7 v 1.9 - - v i o = ? 24 ma; v cc = 3.0 v 2.0 - - v i o = ? 32 ma; v cc = 4.5 v 3.4 - - v v ol low-level output voltage v i = v ih or v il i o = 100 a; v cc = 1.65 v to 5.5 v - - 0.1 v i o = 4 ma; v cc = 1.65 v - - 0.70 v i o = 8 ma; v cc = 2.3 v - - 0.45 v i o = 12 ma; v cc = 2.7 v - - 0.60 v i o = 24 ma; v cc = 3.0 v - - 0.80 v i o = 32 ma; v cc = 4.5 v - - 0.80 v i i input leakage current v i = 5.5 v or gnd; v cc =0vto5.5v - - 20 a i off power-off leakage current v i or v o = 5.5 v; v cc = 0 v - - 20 a i cc supply current v i = 5.5 v or gnd; v cc =1.65vto5.5v; i o =0a --40 a i cc additional supply current per pin; v i = v cc ? 0.6 v; i o = 0 a; v cc = 2.3 v to 5.5 v --5000 a table 7. static characteristics ?continued at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 7 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 11. dynamic characteristics [1] typical values are measured at nominal v cc and at t amb = 25 c. [2] t pd is the same as t plh and t phl [3] c pd is used to determine the dynamic power dissipation (p d in w). p d = c pd v cc 2 f i n + (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; (c l v cc 2 f o ) = sum of outputs. 12. waveforms table 8. dynamic characteristics voltages are referenced to gnd (gr ound 0 v); for test circuit see figure 9 . symbol parameter conditions ? 40 c to +85 c ? 40 c to +125 c unit min typ [1] max min max t pd propagation delay na, nb to ny; see figure 8 [2] v cc = 1.65 v to 1.95 v 1.2 3.5 8.6 1.2 10.8 ns v cc = 2.3 v to 2.7 v 0.7 2.3 4.8 0.7 6.0 ns v cc = 2.7 v 0.7 3.0 5.6 0.7 7.0 ns v cc = 3.0 v to 3.6 v 0.7 2.2 4.3 0.7 5.4 ns v cc = 4.5 v to 5.5 v 0.5 1.8 3.3 0.5 4.2 ns c pd power dissipation capacitance per gate; v i = gnd to v cc [3] -14-- -pf measurement points are given in table 9 . v ol and v oh are typical output voltage levels that occur with the output load. fig 8. input (na, nb) to output (ny) propagation delays 001aae9 72 na, nb input ny output t plh t phl gnd v i v m v m v oh v ol
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 8 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate table 9. measurement points supply voltage input output v cc v m v m 1.65 v to 1.95 v 0.5v cc 0.5v cc 2.3 v to 2.7 v 0.5v cc 0.5v cc 2.7 v 1.5 v 1.5 v 3.0 v to 3.6 v 1.5 v 1.5 v 4.5 v to 5.5 v 0.5v cc 0.5v cc test data is given in table 10 . definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = test voltage for switching times. fig 9. test circuit for measuring switching times v ext v cc v i v o 001aae2 35 dut c l r t r l r l pulse generator v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f table 10. test data supply voltage input load v ext v cc v i t r , t f c l r l t plh , t phl 1.65 v to 1.95 v v cc 2.0 ns 30 pf 1 k open 2.3 v to 2.7 v v cc 2.0 ns 30 pf 500 open 2.7 v 2.7 v 2.5 ns 50 pf 500 open 3.0 v to 3.6 v 2.7 v 2.5 ns 50 pf 500 open 4.5 v to 5.5 v v cc 2.5 ns 50 pf 500 open
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 9 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 13. package outline fig 10. package outline sot505-2 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (1) z (1) references outline version european projection issue date iec jedec jeita mm 0.15 0.00 0.95 0.75 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.70 0.35 8 0 0.13 0.1 0.2 0.5 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 0.47 0.33 sot505-2 - - - 02-01-16 w m b p d z e 0.25 14 8 5 a 2 a 1 l p (a 3 ) detail x a l h e e c v m a x a y 2.5 5 mm 0 scale t ssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505 -2 1.1 pin 1 index
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 10 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate fig 11. package outline sot765-1 (vssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) references outline version european projection issue date iec jedec jeita mm 0.15 0.00 0.85 0.60 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.1 8 0 0.13 0.1 0.2 0.4 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.40 0.15 q 0.21 0.19 sot765-1 mo-187 02-06-07 w m b p d z e 0.12 14 8 5 a 2 a 1 q l p (a 3 ) detail x a l h e e c v m a x a y 2.5 5 mm 0 scale vssop8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm sot765 -1 1 pin 1 index
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 11 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate fig 12. package outline sot833-1 (xson8) terminal 1 index area references outline version european projection issue date iec jedec jeita sot833-1 - - - mo-252 - - - sot833 -1 07-11-14 07-12-07 dimensions (mm are the original dimensions) x son8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 e 1 0 1 2 mm scale notes 1. including plating thickness. 2. can be visible in some manufacturing processes. unit mm 0.25 0.17 2.0 1.9 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.5 0.6 a (1) max 0.5 0.04 1 8 2 7 3 6 4 5 8 (2) 4 (2) a
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 12 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate fig 13. package outline sot1089 (xson8) references outline version european projection issue date iec jedec jeita sot1089 mo-252 sot1089_po 10-04-09 10-04-12 unit mm max nom min 0.5 0.04 1.40 1.35 1.30 1.05 1.00 0.95 0.55 0.35 0.35 0.30 0.27 a (1) dimensions note 1. including plating thickness. 2. visible depending upon used manufacturing technology. x son8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm sot108 9 a 1 bl 1 0.40 0.35 0.32 0.20 0.15 0.12 deee 1 l 0 0.5 1 mm scale terminal 1 index area e d detail x a a 1 l l 1 b e 1 e terminal 1 index area 1 4 8 5 (4 ) (2) (8 ) (2) x
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 13 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate fig 14. package outline sot996-2 (xson8u) references outline version european projection issue date iec jedec jeita sot996-2 - - - - - - sot996- 2 07-12-18 07-12-21 unit a max mm 0.5 0.05 0.00 0.35 0.15 3.1 2.9 0.5 1.5 0.5 0.3 0.6 0.4 0.1 0.05 a 1 dimensions (mm are the original dimensions) x son8u: plastic extremely thin small outline package; no leads; 8 terminals; utlp based; body 3 x 2 x 0.5 mm 0 1 2 mm scale b d 2.1 1.9 e e e 1 l l 1 0.15 0.05 l 2 v w 0.05 y y 1 0.1 c y c y 1 x b 14 85 e 1 e a c b v m c w m l 2 l 1 l terminal 1 index area b a d e detail x a a 1
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 14 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate fig 15. package outline sot902-1 (xqfn8u) references outline version european projection issue date iec jedec jeita sot902-1 mo-255 - - - - - - sot902- 1 05-11-25 07-11-14 unit a max mm 0.5 a 1 0.25 0.15 0.05 0.00 1.65 1.55 0.35 0.25 0.15 0.05 dimensions (mm are the original dimensions) x qfn8u: plastic extremely thin quad flat package; no leads; 8 terminals; utlp based; body 1.6 x 1.6 x 0.5 mm b dl e 1 1.65 1.55 e e l 1 v 0.1 0.55 0.5 w 0.05 y 0.05 0.05 y 1 0 1 2 mm scale x c y c y 1 terminal 1 index area terminal 1 index area b a d e detail x a a 1 b 8 7 6 5 e 1 e 1 e e a c b ? v m c ? w m 4 1 2 3 l l 1 metal area not for soldering
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 15 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate fig 16. package outline sot1116 (xson8) references outline version european projection issue date iec jedec jeita sot1116 sot1116_po 10-04-02 10-04-07 unit mm max nom min 0.35 0.04 1.25 1.20 1.15 1.05 1.00 0.95 0.55 0.3 0.40 0.35 0.32 a (1) dimensions note 1. including plating thickness. 2. visible depending upon used manufacturing technology. x son8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm sot111 6 a 1 b 0.20 0.15 0.12 deee 1 l 0.35 0.30 0.27 l 1 0 0.5 1 mm scale terminal 1 index area e d (4 ) (2) (8 ) (2) a 1 a e 1 e 1 e 1 e l l 1 b 4 3 2 1 5 6 7 8
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 16 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate fig 17. package outline sot1203 (xson8) references outline version european projection issue date iec jedec jeita sot1203 sot1203_po 10-04-02 10-04-06 unit mm max nom min 0.35 0.04 1.40 1.35 1.30 1.05 1.00 0.95 0.55 0.35 0.40 0.35 0.32 a (1) dimensions note 1. including plating thickness. 2. visible depending upon used manufacturing technology. x son8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm sot120 3 a 1 b 0.20 0.15 0.12 deee 1 l 0.35 0.30 0.27 l 1 0 0.5 1 mm scale terminal 1 index area e d (4 ) (2) (8 ) (2) a a 1 e l l 1 b e 1 e 1 e 1 1 8 2 7 3 6 4 5
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 17 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 14. abbreviations 15. revision history table 11. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 12. revision history document id release date data sheet status change notice supersedes 74lvc2g00_9 20100608 product data sheet - 74lvc2g00_8 modifications: ? added type number 74LVC2G00GF (sot1089/xson8 package). ? added type number 74lvc2g00gn (sot1116/xson8 package). ? added type number 74lvc2g00 gs (sot1203/xson8 package). 74lvc2g00_8 20091026 product data sheet - 74lvc2g00_7 74lvc2g00_7 20080610 product data sheet - 74lvc2g00_6 74lvc2g00_6 20080220 product data sheet - 74lvc2g00_5 74lvc2g00_5 20070904 product data sheet - 74lvc2g00_4 74lvc2g00_4 20060515 product data sheet - 74lvc2g00_3 74lvc2g00_3 20050201 product specification - 74lvc2g00_2 74lvc2g00_2 20040923 product specification - 74lvc2g00_1 74lvc2g00_1 20031117 product specification - -
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 18 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
74lvc2g00_9 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 09 ? 8 june 2010 19 of 20 nxp semiconductors 74lvc2g00 dual 2-input nand gate export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvc2g00 dual 2-input nand gate ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 june 2010 document identifier: 74lvc2g00_9 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 recommended operating conditions. . . . . . . . 5 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 18 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17 contact information. . . . . . . . . . . . . . . . . . . . . 19 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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